Appendix C - Site Drawings: Difference between revisions
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= APU102 Single Track System Diagram = | = APU102 Single Track System Diagram = | ||
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Drawing Number: 601-419I<br> | Drawing Number: 601-419I<br> | ||
= APU-102 Interconnect Drawing, 486SLC CPU w/ USSD = | = APU-102 Interconnect Drawing, 486SLC CPU w/ USSD = | ||
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Drawing Number: 70-0315-00<br> | Drawing Number: 70-0315-00<br> | ||
= APU-102 Interconnect Drawings, Pentium (LPMTX) CPU w/o Network = | = APU-102 Interconnect Drawings, Pentium (LPMTX) CPU w/o Network = | ||
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Drawing Number: 70-0316-00<br> | Drawing Number: 70-0316-00<br> | ||
= APU-102 Interconnect Drawings, Pentium (LPMTX) CPU with Network = | = APU-102 Interconnect Drawings, Pentium (LPMTX) CPU with Network = | ||
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Drawing Number: 70-0316-01<br> | Drawing Number: 70-0316-01<br> | ||
= APU-102 Interconnect Drawings, LX800 CPU w/ COM4N = | = APU-102 Interconnect Drawings, LX800 CPU w/ COM4N = | ||
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Drawing Number: 70-0316-02<br> | Drawing Number: 70-0316-02<br> | ||
= APU-102 Interconnect Drawings, LX800 CPU w/ LX-COM = | = APU-102 Interconnect Drawings, LX800 CPU w/ LX-COM = | ||
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Drawing Number: 70-0316-03 | Drawing Number: 70-0316-03 | ||
Latest revision as of 19:32, 31 October 2024
Railnet AEI System Site Installation Manual
The following are site installation drawings listed in the order they would likely be used at a site.
These drawings are for reference only and are not intended to be a comprehensive drawing package. Depending on customer practices and/or age of AEI site, trackside junctions may use telephone type pedestal, antenna tower junction box, signal junction box, underground junction box or may be home run to equipment enclosure/hut.
Refer to your customer specific practices and drawings for site specific installation information.
| Drawing Name | Drawing Number |
| SLU/SHU Single Track Low/High Speed Unrestricted System Perspective | 101-01 |
| SLU/SHU Single Track Low/High Speed Unrestricted Site Layout with Splice Pedestal | 101-02 |
| SLU/SHU AEI Site Elevation | 101-03 |
| SLU/SHU Grounding Plan | 101-04 |
| Single Track Loop Layout | 101-05 |
| DC Protection Terminal Blocks SLU/SHU | 101-06 |
| SLU/SHU AEI System Flow – Tiefenbach Transducers | 101-07 |
| Tiefenbach Sensor Installation Detail | 101-08 |
| Junction/Pull Box A10R106CA w/CASH132A-LT3 | 101-09 |
| Loop Detector Front Panel (913AI) | 101-10 |
| Erico Ground Panel Assembly Detail | 101-11 |
| Presence Loop – System Flow – Zero Speed Transducer | 101-12 |
| Parapanel Antenna Mounting Detail | 101-13 |
| Check Tag Wiring Detail | 101-14 |
| DLR/DMR Double Track Low/Medium Speed Restrictive System Perspective | 101-15 |
| DLR/DMR & Double Track Low/Medium Speed Restricted Site Layout | 101-16 |
| DHR Double Track High Speed Restrictive System Perspective | 101-17 |
| DHR Double Track High Speed Restricted Site Layout | 101-18 |
| DLR/DMR Antenna Elevation Detail w/Conduit Detail (Signal height) | 101-19 |
| DLR/DMR Antenna Elevation Detail w/Conduit Detail (Alternate mounting for Narrow Track Centers) | 70-5284-06 |
| DHR Antenna Elevation Detail w/ Conduit Detail (Signal height) | 101-20 |
| DLR/DMR/DHR Grounding Plan | 101-21 |
| Double Track Loop Layout | 101-22 |
| DLR, DMR, DHR AEI System Flow – Tiefenbach Transducers | 101-23 |
| DLR, DMR, DHR, AEI Double Track Communications | 101-24 |
| SLU/SHU AEI System Flow – Tiefenbach Transducers for Route indication | 101-26 |
| LVD-2000 Wiring Diagram | 70-0178-00 |
| DLR, DMR, DHR, DMU and DLU AEI – LVD-2000 System Flow | 70-0180-00 |
| DLR, DMR, DHR AEI System Flow – Tiefenbach Transducers and Epic III Presence Circuit | 70-0093-00 |
| SLU/SHU AEI System Flow – Tiefenbach Transducer, ARMS Power Supply, SuppressSurge Protection Panel, and Epic III Presence Circuit | 70-0187-02 |
| APU102 Single Track System Diagram | 601-419I |
| APU-102 Interconnect Drawing, 486SLC CPU w/ USSD | 70-0315-00 |
| APU-102 Interconnect Drawings, Pentium (LPMTX) CPU w/o Network | 70-0316-00 |
| APU-102 Interconnect Drawings, Pentium (LPMTX) CPU with Network | 70-0316-01 |
| APU-102 Interconnect Drawings, LX800 CPU w/ COM4N | 70-0316-02 |
| APU-102 Interconnect Drawings, LX800 CPU w/ LX-COM | 70-0316-03 |
SLU/SHU Single Track Low/High Speed Unrestricted System Perspective
Drawing Number: 101-01
SLU/SHU Single Track Low/High Speed Unrestricted Site Layout
Drawing Number: 101-02
SLU/SHU AEI Site Elevation
Drawing Number: 101-03
SLU/SHU Grounding Plan
Drawing Number: 101-04
Single Track Loop Layout
Drawing Number: 101-05
DC Protection Terminal Blocks SLU/SHU
Drawing Number: 101-06
SLU/SHU AEI System Flow – Tiefenbach Transducers
Drawing Number: 101-07
Tiefenbach Sensor Installation Detail
Drawing Number: 101-08
Junction/Pull Box A10R106CA w/CASH132A-LT3
Drawing Number: 101-09
Loop Detector Front Panel
Drawing Number: 101-10
Erico Ground Panel Assembly Detail
Drawing Number: 101-11
Presence Loop – System Flow – Typical
Drawing Number: 101-12
Parapanel Antenna Mounting Detail
Drawing Number: 101-13
Check Tag Wiring Detail
Drawing Number: 101-14
DLR/DMR Double Track Low/Medium Speed Restrictive System Perspective
Drawing Number: 101-15
DLR/DMR & Double Track Low/Medium Speed Restricted Site Layout
Drawing Number: 101-16
DHR Double Track High Speed Restrictive System Perspective
Drawing Number: 101-17
DHR Double Track High Speed Restricted Site Layout
Drawing Number: 101-18
DLR/DMR Antenna Elevation Detail w/Conduit Detail (Signal height)
Drawing Number: 101-19
DLR/DMR Antenna Elevation Detail w/Conduit Detail (Alternate mounting for Narrow Track Centers)
Drawing Number: 70-5284-06
DHR Antenna Elevation Detail w/ Conduit Detail (Signal height)
Drawing Number: 101-20
DLR/DMR/DHR Grounding Plan
Drawing Number: 101-21
Double Track Loop Layout
Drawing Number: 101-22
DLR, DMR, DHR AEI System Flow – Tiefenbach Transducers
Drawing Number: 101-23
DLR, DMR, DHR, AEI Double Track Communications
Drawing Number: 101-24
SLU/SHU AEI System Flow – Tiefenbach Transducers for Route indication
Drawing Number: 101-26
LVD-2000 Wiring Diagram
Drawing Number: 70-0178-00
DLR, DMR, DHR, DMU and DLU AEI – LVD-2000 System Flow
Drawing Number: 70-0180-00
DLR, DMR, DHR AEI System Flow – Tiefenbach Transducers and Epic III Presence Circuit
Drawing Number: 70-0093-00
SLU/SHU AEI System Flow – Tiefenbach Transducer, ARMS Power Supply, SuppressSurge Protection Panel, and Epic III Presence Circuit
Drawing Number: 70-0187-02
APU102 Single Track System Diagram
Drawing Number: 601-419I
APU-102 Interconnect Drawing, 486SLC CPU w/ USSD
Drawing Number: 70-0315-00
APU-102 Interconnect Drawings, Pentium (LPMTX) CPU w/o Network
Drawing Number: 70-0316-00
APU-102 Interconnect Drawings, Pentium (LPMTX) CPU with Network
Drawing Number: 70-0316-01
APU-102 Interconnect Drawings, LX800 CPU w/ COM4N
Drawing Number: 70-0316-02
APU-102 Interconnect Drawings, LX800 CPU w/ LX-COM
Drawing Number: 70-0316-03